This invention relates to a method of fabricating semiconductor devices, and more particularly, MOS devices in integrated circuits.
There is a continuing effort in the semiconductor integrated circuit art to achieve greater device densities and increased operating speeds, both of which are enhanced by making each individual device smaller. In the field of MOS memories in particular, memory capacity is directly related to the number of devices and thus for a given size semiconductor chip, greater device density means greater memory capacity. Generally, smaller devices have been achieved by reducing the feature size in planar devices using improved photolithography. However, as feature size approaches one micron, the practical limits of the photolithographic art are being encountered where adequate pattern definition is extremely difficult and costly to achieve.
Reduction in MOS device dimensions, particularly the important dimension of channel length, has been achieved in planar devices by fabrication of the so-called double-diffused MOS (DMOS) devices such as are disclosed in U.S. Pat. No. 3,950,777. The planar DMOS structure does not have a self-aligned gate and as a consequence exhibits high gate-to-source and gate-to-drain capacitances. In addition, the drain drift space requires precise lateral dimensional control and entails more masking steps than conventional planar MOS devices.
The double implanted MOS structure disclosed by J. Tihanyi and D. Widmann, Technical Digest, 1977, IEEE, IEDM, Washington, D.C., page 399, eliminates the disadvantage of high gate-to-source capacitance. It is, however, basically a planar MOS device with lateral dimensional control problems.
Thus an object of this invention is an MOS device which is smaller in size and is achieved with a high degree of precision without straining the limits of the photolithographic art.